The present invention relates to flip-flop circuits, and in particular to flip-flop circuits having low set up and hold time characteristics.
Flip-flop circuits are widely used in digital electronic circuits. Examples of conventional flip-flop circuit configurations include D-type, JK-type, and master-slave type devices.
FIG. 1(a) shows the logic diagram of a master-slave type flip-flop 100 comprising a master latch 102 and a slave latch 104. Master latch 102 receives a data input signal DATA_IN on a data input terminal. Slave latch 104 includes a data input coupled to a data output Q1 of master latch 102 and receives a clock input signal CLK1′ which is the complement of clock signal CLK1.
FIG. 1(b) shows the timing diagram of the master-slave type flip-flop 100. On the active edge 110 of clock input signal CLK1, which in this example is a rising edge, the master latch 102 transmits the data input signal DATA_IN to data output terminal Q1 after a time delay representing the propagation delay of the master latch 102. Slave latch 104 ignores changes to data output Q1 until the falling edge 112 of the clock input signal CLK1, which corresponds with the rising edge of inverted clock signal CLK1′.
On the falling edge of the clock input signal CLK1, the data output at data output terminal Q1 is transmitted to output terminal Q as DATA_OUT after a time delay representing the propagation delay of the slave latch 104. The master latch 102 thus latches the data input signal DATA_IN when the clock signal CLK1 is in a first state and the slave latch 104 latches the data output signal from the master latch 102 when the clock signal CLK1 is in a second state.
For a master slave flip-flop 100 to function predictably, data input signal DATA_IN must satisfy two timing constraints, namely, a setup time and a hold time, relative to active edges of clock input signal CLK1. The setup time is the minimum time that data input signal DATA_IN must be held valid prior to an active clock edge. The hold time is the minimum time that data input signal DATA_IN must be held valid after an active clock edge. If either the setup time or hold time requirement is not satisfied, the data output signal DATA_OUT of master-slave type flip-flop 100 is undeterminable and may result in a metastable condition.
Flip-flops circuits with long setup and hold time requirements thus present an obstacle to increasing clock frequency, and therefore to improving the performance of digital circuits. Hence, it is becoming increasingly important to implement flip-flop circuits having relatively low setup and hold time requirements.
Higher speed flip-flops have been created by employing pulse-triggered flip-flops which incorporate pulse-generating circuits for converting a clock signal into a pulse signal having a width less than that of the clock signal. Pulse-triggered circuits may be implemented using a single latch and thus require less area, and lower power requirements as compared to conventional master-slave flip-flops.
FIG. 2(a) shows the logic diagram of a pulse-triggered flip-flop 200 having a data input terminal D1 for receiving data input signal DATA_IN, a clock input terminal, and a data output terminal Q1. Pulse-generation circuit 202 includes a series arrangement 204 of inverters and XNOR gate 206. Clock input signal CLK1 is passed to the input ‘A’ of XNOR gate 206 and included in a logical XNOR operation with the delayed and inverted data signal at input ‘B’ of XNOR gate 206.
FIG. 2(b) shows the timing diagram of pulse-generation circuit 202. The output at XNOR gate 206 provides a clock input to register 208 as a pulse signal (PULSE) having a pulse width (W) that depends on the total propagation delay (Tpd) introduced by the inverter arrangement 204.
The total propagation delay (Tpd) provided by the inverter arrangement 204, and thus the width (W) of the pulse signal, depends on the propagation delay of each inverter in the inverter arrangement 204, which in turn is susceptible to process-voltage-temperature (PVT) variations. These PVT related variations lead to stringent setup and hold time requirements which place constraints on the data input signal. The constraints depend on a “worst” case PVT variation and a “best” case PVT variation. For example, for the “worst” case PVT variation, meaning the PVT case where the propagation delay (Tpd) is highest and thus the pulse width (W) is wider, data input signal DATA_IN is required to be held constant for a longer duration. On the other hand, for the “best” case PVT variation, where the propagation delay (Tpd) is lowest and thus the pulse width (W) is narrower, the slew rate of data signal DATA_IN is required to be higher. If either of these conditions are not satisfied, a race condition will occur.
A need exists for a flip-flop circuit that avoids the set up time requirement and provides a reduced hold time requirement.